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IEEE International Symposium on Design and Diagnostics of Electronic Circuit and Systems
(DDECS19)
April 24-26, 2019
Cluj-Napoca, Romania

http://www.lirmm.fr/ddecs2019/

SUBMISSION DEADLINE JANUARY 14th, 2019
CALL FOR PAPERS

Scope

The IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems provides a forum for exchanging ideas, discussing research results, and presenting practical applications in the areas of design, test, and diagnosis of electronic circuits and systems. The DDECS Symposium series has been organized by these European countries: Hungary (2001, 2005, 2018), Austria (2010), Germany (2011,2017), Estonia (2012), Czech Republic (1997, 2002, 2006, 2009, 2013), Poland (1998, 2003, 2007, 2014), Serbia (2015) and Slovakia (2000, 2004, 2008, 2016).

Submissions

DDECS’19 covers the areas of design and testing of electronic components, both digital and analog. The topics include the following but are not limited to:

  • SoC and NoC Design and Test
  • ASIC/FPGA Design
  • Built-in Self-Test and Self-Repair
  • Bio-Inspired Hardware
  • Design Verification/Validation
  • Formal Methods in System Design
  • Hardware/Software Co-Design
  • IP-based Design
  • Logic Synthesis
  • Modeling, circuit design and test for emerging technologies-based data storage/memory
  • Modeling, circuit design and test for emerging technologies-based computation structures
  • Defect/Fault Tolerance and Reliability
  • Design and Test in Nano-Technologies
  • Analog, Mixed-Signal, RF Design and Test
  • ATE Hardware and Software
  • Design for Testability and Diagnosis
  • Embedded Systems
  • Dependable HW / SW Systems
  • On-line Testing
  • Memory, Processor Testing
  • MEMS Testing
  • Physical Design
  • Cyber Physical Systems
  • Industry 4.0
  • Embedded Machine Learning
  • Self-Aware Systems Design and Test
  • Unconventional Computing Paradigms
  • Emerging technologies-based logic design, test and reliability
  • Internet-of-Things Design and Test
  • Case Studies and Applications
  • Functional Safety
  • Reliability testing
  • Hardware Security and Trust
  • Security Primitives
  • Hardware Trojans
  • Fault and Side-Channel Attacks and Countermeasures
  • Hardware Security and Emerging Technologies

Key Dates

Submission Deadline: January 14, 2019
Notification of Acceptance: March 15, 2019
Camera-ready Papers: April 1, 2019
Additional Information
General formation:
Liviu Miclea (General Chair)
TECHNICAL UNIVERSITY OF CLUJ-NAPOCA, ROMANIA
Email: Liviu.Miclea@aut.utcluj.ro

Program information:
Alberto Bosio (Program Chair)
INL – ECOLE CENTRALE DE LYON – CNRS, FRANCE
Email: alberto.bosio@ec-lyon.fr
Committee


General Chair
  • Liviu Miclea - TECHNICAL UNIVERSITY OF CLUJ-NAPOCA, ROMANIA

Program Chair
  • Alberto Bosio - INL – ECOLE CENTRALE DE LYON – CNRS, FRANCE

General Vice-Chair:
  • György Cserey - PÁZMÁNY PÉTER CATHOLIC UNIVERSITY, BUDAPEST, HUNGARY

Program Vice-Chair:
  • Zoran Stamenkovic - IHP – FRANKFURT (ODER), GERMANY

Publication Chair:
  • Alessandro Savino - Politecnico di Torino, Italy
 
Publicity Chair:
  • Ernesto Sanchez - Politecnico di Torino, Italy
 
Publicity Chair:
  • Mario Barbareschi - University of Naples “Federico II”, Italy
 
Web Chair:
  • Marcello Traiola - LIRMM – UNIVERSITY OF MONTPELLIER – CNRS, FRANCE 
For more information, visit us on the web at: http://www.lirmm.fr/ddecs2019/

The IEEE International Symposium on Design and Diagnostics of Electronic Circuit and Systems  is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).



IEEE Computer Society-Test Technology Technical Council

TTTC CHAIR
Chen-Huan CHIANG
Intel - USA
E-mail chen-huan.chiang@intel.com

PAST CHAIR
Michael NICOLAIDIS
TIMA laboratory - France
E-mail michael.nicolaidis@imag.fr

TTTC 1ST VICE CHAIR
Matteo SONZA REORDA
Politecnico di Torino - Italy
E-mail matteo.sonzareorda@polito.it

SECRETARY
Joan FIGUERAS
Un. Politec. de Catalunya - Spain
E-mail figueras@eel.upc.es

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Paolo BERNARDI

Politecnico di Torino
- Italy
E-mail paolo.bernardi@polito.it

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
E-mail rkapur@synopsys.com

EUROPE
Giorgio DI NATALE
LIRMM - France
E-mail giorgio.dinatale@lirmm.fr

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Giorgio DI NATALE
LIRMM - France
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
Adith SINGH
Auburn University – USA
E-mail adsingh@eng.auburn.edu

TTTC 2ND VICE CHAIR
Rohit KAPUR
Synopsys, Inc. – USA
E-mail rkapur@synopsys.com

FINANCE
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com


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